The NAND (short for "not and") gate is a favorite of computer hardware designers. This is because all of the standard logical operations (negation, and, or, implication, and exclusive or) can be achieved using only NAND gates. Microprocessor chips can therefore be built with only one kind of gate.
Let NAND(A,B) stand for the logical statement ¬(A∧B).
Then NAND(A,A) ⇔ ¬(A∧A) ⇔ ¬A.
NAND[NAND(A,B), NAND(A,B)] ⇔ ¬NAND(A,B) ⇔ A ∧ B.
NAND[NAND(A,A), NAND(B,B)] ⇔ NAND(¬A,¬B) ⇔ ¬(¬A&¬B) ⇔ A ∨ B.
NAND[A, NAND(B,B)] ⇔ NAND(A,¬B) ⇔ ¬(A∧¬B) ⇔ ¬A ∨ B ⇔ A ⇒ B.
NAND{NAND[A, NAND(B,B)], NAND[B, NAND(A,A)]} ⇔ NAND[NAND(A,¬B), NAND(B,¬A)] ⇔ ¬[¬(A∧¬B) ∧ ¬(B∧¬A)] ⇔ (A∧¬B) ∨ (B∧¬A) ⇔ A | B.
The NOR ("not or") operator can accomplish the same tasks, although implication requires an extra step.
Let NOR(A,B) stand for the statement ¬(A∨B).
Then NOR(A,A) ⇔ ¬(A∨A) ⇔ ¬A.
NOR[NOR(A,A), NOR(B,B)] ⇔ NOR(¬A,¬B) ⇔ ¬(¬A ∨ ¬B) ⇔ A ∧ B.
NOR[NOR(A,B), NOR(A,B)] ⇔ ¬NOR(A,B) ⇔ A ∨ B.
NOR{NOR[NOR(A,A),B], NOR[NOR(A,A),B]} ⇔ ¬NOR[NOR(A,A),B] ⇔ ¬A ∨ B ⇔ A ⇒ B.
NOR{NOR[A, NOR(B,B)], NOR[B, NOR(A,A)]} ⇔ NOR[NOR(A,¬B), NOR(B,¬A)] ⇔ ¬[¬(A∨¬B) ∨ ¬(B∨¬A)] ⇔ (A∨¬B) ∧ (B∨¬A) ⇔ A | B.
Notes: In the schemes above, all logical operations with the exception of implication require the same number of gates, whether using NAND or NOR.
Negation and exclusive or are accomplished in the same way with both gates. Not surprisingly, and can be accomplished with NAND gates in the same way that or is accomplished with NOR, and conversely, or can be accomplished with NAND gates in the same way that and is accomplished with NOR.
It appears, however, that NAND and NOR are fundamentally different as building blocks of logical design. In the schemes above, implication is accomplished with five NOR gates, whereas only three NAND gates are required to accomplish the same task. This is presumably why NAND is preferred as the more efficient of the two.
I haven't proved that the number of gates required for achieving implication in either of the schemes described above is minimal.